The present invention relates to a CMOS (Complementary Metal-oxide Semiconductor) type semiconductor device having a gate electrode of p type and n type conductive polycrystalline silicon and a method of manufacture thereof.
The current trend of the semiconductor device has been changed from a CMOS semiconductor device whose gate electrode is composed of only polycrystalline silicon containing an n-type impurity into the so-called dual gate CMOS semiconductor device in which the gate electrode of an n-channel MOS transistor is composed of polycrystalline silicon containing an n-type impurity and the gate electrode of a p-channel MOS transistor is composed of polycrystalline silicon containing a p-type impurity. This dual gate contains a silicon oxide film, a silicon nitride film or resist coated on the surface of the polycrystalline silicon except a target area. A target area (for example, n-type) impurity is implanted in the non-coated area with these films as a mask by means of the ion-implantation technique or the diffusion technique. After removing this mask materials, the surface of the polycrystalline silicon on the area having the above-mentioned impurity is covered with the similar mask materials. The impurity having the opposite conductive type (for example, p type) to the above-mentioned impurity is implanted in the non-covered area by means of the ion-implantation technique.
For dividing the polycrystalline area into an n+ and a p+ conductive areas, as mentioned above, a mask material is formed on a specific area in doping a target impurity, which needs two associative processes of forming a mask. It is thus necessary to perform each process of forming a mask film, doing photolithography, and dry-etching a mask film twice. It means that the dual gate CMOS semiconductor composed as above has more manufacturing steps than the CMOS semiconductor device composed of polycrystalline silicon containing only one conductive impurity. This brings about the lowering of a manufacturing yield and the rise of a manufacturing cost of the semiconductor device and therefore the rise of a product cost. Further, the slip of fitting the mask patterns may be brought about in dividing the n-type and the p-type areas in the photolithography process. Hence, the fitting allowance is required, which has been an obstacle to finning the element and enhancing the concentration of the semiconductor device.
On the other hand, the MOS transistor having as a component of a gate electrode polycrystalline silicon or amorphous silicon film containing boron has a shortcoming that by performing a high temperature annealing with respect to the MOS transistor after forming the gate electrode, the boron is diffused from the gate electrode into a gate oxide film, in a worse case, penetrates the gate oxide film and reaches the silicon substrate, thereby causing a threshold voltage of the transistor to shift from a design value. It has been reported that the annealing in a hydrogen atmosphere diffuses boron through the gate oxide film faster than the annealing in a nitrogen atmosphere. (IEEE Electron Device Let., Vol.17, No.11, pp497 to 499)
In order to enhance the integration of the semiconductor device, the need for development of an SAC (Self-aligned contact) technique has risen. This SAC technique is composed by covering the gate electrode with a silicon nitride film and a silicon oxide serving as an insulating film between a gate electrode and the upper metal layer for an interconnection on the silicon nitride. Then, a contact hole, which is served as connecting the source and the drain of the MOS type semiconductor device with the electrode wiring, is formed by the dry-etching technique. In this dry-etching technique, the process is conditioned in order to make the etching speed of the silicon oxide faster than that of the silicon nitride. As a result, if the deviation of the designed position of a contact hole to a gate electrode pattern is brought about in the photolithography process, no short takes place between the gate electrode and the source or the drain.
The silicon nitride film that is important to this SAC technique is generally formed by means of the CVD (Chemical Vapor Deposition). This silicon nitride film contains several percents to 20 percents of hydrogen. This hydrogen serves to accelerate leakage of boron contained in the polycrystalline silicon layer into the substrate. In an extreme case, the amount of boron to be leaked through the gate oxide film is made so large that the channel area n-type silicon substrate of the p-channel MOS transistor is inverted into the p-type one.